Memory cell, memory cell arrangement, and methods thereof

A memory cell arrangement comprising:

• a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a source-line node, a bit-line node, a word-line node, and an operating-line node;
• a field-effect transistor memory structure comprising a field-effect transistor structure and memory element, the memory element comprising a spontaneously polarizable layer, wherein a first source/drain node of the field-effect transistor memory structure is coupled to the source-line node, and wherein a second source/drain node of the field-effect transistor memory structure is coupled to the bit-line node;
• and
• an access device, coupled to a gate of the field-effect transistor memory structure, to the word-line node, and to the operating-line node, wherein the access device is configured to control a voltage at the gate of the field-effect transistor memory structure on both a word-line voltage provided at the word-line node and an operating-line voltage provided at the operating-line node;
• a memory control circuit configured to write a selected memory cell of the plurality of memory cells and to inhibit writing of one or more non-selected memory cells of the plurality of memory cells by a pre-write operation and a write operation subsequent to the pre-write operation.

A method for writing a selected memory cell of a memory cell arrangement, the memory cell arrangement comprising:

• a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a field-effect transistor memory structure connecting a source-line node and a bit-line node of the memory cell with one another, and
• an access field-effect transistor structure coupled to the field-effect transistor memory structure to control a voltage at a gate of the field-effect transistor memory structure as a function of both a word-line voltage provided to the access field-effect transistor structure via a word-line node of the memory cell and an operating-line voltage provided to the access field-effect transistor structure via an operating-line node of the memory cell;
• the method comprising:
• writing the selected memory cell by pre-charge operation and a subsequent write operation corresponding to the pre-charge operation,
• wherein a respective gate of one or more of the field-effect transistor memory structures of the plurality of memory cells is pre-charged to a predefined voltage level by the pre-charge operation, and
• wherein the selected memory cell of a memory cell arrangement is written by the subsequent write operation and wherein a writing of one or more non-selected memory cells of the memory cell arrangement is inhibited during the subsequent write operation.

A memory cell arrangement comprising:

• a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
• a source-line node, a bit-line node, a word-line node, and an operating-line node;
• a field-effect transistor memory structure comprising a field-effect transistor structure and memory element, the memory element comprising a spontaneously polarizable layer, wherein a first source/drain node of the field-effect transistor memory structure is coupled to the source-line node, and wherein a second source/drain node of the field-effect transistor memory structure is coupled to the bit-line node;
• and
• an access device, coupled to a gate of the field-effect transistor memory structure, to the word-line node, and to the operating-line node, wherein the access device is configured to control a voltage at the gate of the field-effect transistor memory structure on both a word-line voltage provided at the word-line node and an operating-line voltage provided at the operating-line node;
• and
• wherein memory cells of a subset of the plurality of memory cells share at least one of:
• a word-line electrically connected to respective word-line nodes of the memory cells of the subset,
• a source-line electrically connected to respective source-line nodes of the memory cells of the subset,
• a bit-line electrically connected to respective bit-line nodes of the memory cells of the subset, and/or
• an operating-line electrically connected to respective operating-line nodes of the memory cells of the subset.