Memory device

A memory device, comprising:

• a memory group, comprising a plurality of memory banks;
• and
• a control circuit, coupled to the memory group, wherein the control circuit comprises:
• a tri-state logic enable circuit, configured to temporarily store a plurality of temporarily stored address signals, to output the plurality of temporarily stored address signals according to a synchronization signal, to decode the plurality of temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the plurality of memory banks;
• the tri-state logic enable circuit comprises a first sequence circuit, configured to generate a plurality of indicator signals according to the synchronization signal and a read signal, the first sequence circuit comprises:
• a first flip flop sequence, comprising a plurality of D flip flops, wherein a first D flip flop of the plurality of D flip flops comprises:
• an output terminal, configured to output a first indicator signal of the plurality of indicator signals;
• a first input terminal, configured to receive a second indicator signal of the plurality of indicator signals output by a second D flip flop of the plurality of D flip flops or a third indicator signal of the plurality of indicator signals output by a third D flip flop of the plurality of D flip flops, wherein the first D flip flop is connected in serious between the second flip flop and the third flip flop;
• a second input terminal, configured to receive one of the read signal and the synchronization signal;
• and
• a third input terminal, configured to receive a preset signal;
• and
• an address decoding circuit, configured to decode the plurality of temporarily stored address signals to drive the one of the plurality of memory banks.