Reference-voltage-generators within integrated assemblies

An integrated assembly, comprising:

• a memory region comprising memory cells and sense/access lines configured for addressing the memory cells;
• a reference-voltage-generator proximate the memory region;
• the reference-voltage-generator including resistive units configured substantially identically to the sense/access lines;
• resistive components configured to each comprise two of the resistive units paired to one another;
• there being at least three of the resistive components, with said three of the resistive components being a first resistive component, a second resistive component and a third resistive component;
• a first conductive interconnect coupling the first resistive component in series to the second resistive component;
• a second conductive interconnect coupling the second resistive component in series to the third resistive component;
• and
• switching circuitry configured to selectively couple the first and second interconnects to a reference voltage output.

An integrated assembly, comprising:

• a memory region comprising memory cells, digit lines and wordlines;
• each of the memory cells being uniquely addressed with one of the wordlines in combination with one of the digit lines;
• the wordlines being coupled with driver circuitry;
• and
• a reference-voltage-generator proximate the memory region;
• the reference-voltage-generator including resistive units configured substantially identically to the wordlines, the resistive units comprising a first resistive unit and a second resistive unit coupled to the first resistive unit through a conductive interconnect.

An integrated assembly, comprising:

• a memory region comprising memory cells, digit lines and wordlines;
• each of the memory cells being uniquely addressed with one of the wordlines in combination with one of the digit lines;
• the wordlines being coupled with driver circuitry;
• a reference-voltage-generator proximate the memory region;
• the reference-voltage-generator including resistive units configured substantially identically to the wordlines;
• resistive components configured to each comprise two or more of the resistive units coupled to one another in series;
• there being at least three of the resistive components, with said three of the resistive components being a first resistive component, a second resistive component and a third resistive component;
• a first conductive interconnect coupling the first resistive component in series to the second resistive component;
• a second conductive interconnect coupling the second resistive component in series to the third resistive component;
• and
• switching circuitry configured to selectively couple the first and second interconnects to a reference voltage output.

An integrated assembly, comprising:

• a memory region comprising memory cells, digit lines and wordlines;
• each of the memory cells being uniquely addressed with one of the wordlines in combination with one of the digit lines;
• the digit lines being coupled with sensing circuitry;
• and
• a reference-voltage-generator proximate the memory region;
• the reference-voltage-generator including resistive units configured substantially identically to the digit lines, the resistive units comprising a first resistive unit and a second resistive unit coupled to the first resistive unit through a conductive interconnect.

An integrated assembly, comprising:

• a memory region comprising memory cells, digit lines and wordlines;
• each of the memory cells being uniquely addressed with one of the wordlines in combination with one of the digit lines;
• the digit lines being coupled with sensing circuitry;
• a reference-voltage-generator proximate the memory region;
• the reference-voltage-generator including resistive units configured substantially identically to the digit lines;
• resistive components configured to each comprise two or more of the resistive units coupled to one another in series;
• there being at least three of the resistive components, with said three of the resistive components being a first resistive component, a second resistive component and a third resistive component;
• a first conductive interconnect coupling the first resistive component in series to the second resistive component;
• a second conductive interconnect coupling the second resistive component in series to the third resistive component;
• and
• switching circuitry configured to selectively couple the first and second interconnects to a reference voltage output.