Semiconductor memory device
AssigneeKioxia Corporation
InventorTakuya Futatsuyama
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region, a second region adjacent to the first region in the first direction, and a third region configured to connect the first region and the second region. The memory cell array further includes: a first insulating layer buried in a first trench between the first region and the second region and in contact with the third region; a first contact plug provided in the first insulating layer and electrically connected to the row decoder; and a first interconnect configured to connect a selection gate line and the first contact plug.
Claims16
A semiconductor memory device comprising:
- a memory cell array including a source line provided above a first surface of a semiconductor substrate, and a word line provided above the source line;
- a wall surrounding the memory cell array in a plane along the first surface, including a plurality of conductive layers arranged in a direction crossing the first surface of the semiconductor substrate from a layer of the source line to a layer of the word line, and including a recess at an inner surface extending from an upper surface to a lower surface;
- and
- an insulating layer provided from a position of the upper surface of the wall to a position of the lower surface and being in contact with the inner surface of the wall in the recess.
A semiconductor memory device comprising:
- a first row decoder provided on a semiconductor substrate;
- a second row decoder provided apart from the first row decoder in a first direction on the semiconductor substrate, the first direction being an in-plane direction of the semiconductor substrate;
- a memory cell array including a first block and a second block provided above the first row decoder and the second row decoder and along a second direction, the second direction differing from the first direction and being the in-plane direction of the semiconductor substrate,
- the first block including
- a first region spreading along a first plane formed by the first direction and the second direction and having a first width along the second direction,
- a second region spreading along the first plane, having a second width larger than the first width along the second direction, and being adjacent to the first region on one side in the first direction, and
- a third region spreading along the first plane, having a third width along the second direction, located between the first region and the second region, and connecting the first region and the second region,
- the second block including:
- a fourth region spreading along the first plane and having a fourth width along the second direction,
- a fifth region spreading along the first plane, having a fifth width lager than the fourth width along the second direction, and being adjacent to the fourth region on another side in the first direction, and
- a sixth region spreading along the first plane, having a sixth width along the second direction, located between the fourth region and the fifth region, and connecting the fourth region and the fifth region,
- the first region, the second region, and the third region including a plurality of first word lines stacked along a third direction, the third direction being a vertical direction of the semiconductor substrate,
- the first region including a first select gate line provided above an uppermost first word line of the plurality of first word lines,
- the fourth region, the fifth region, and sixth region including a plurality of second word lines stacked along the third direction,
- the fourth region including a second select gate line provided above an uppermost second word line of the plurality of second word lines,
- the plurality of first word lines and the first select gate line being electrically connected to the first row decoder, and
- the plurality of second word lines and the second select gate line being electrically connected to the second row decoder;
- and
- a wall surrounding the memory cell array along the in-plane direction of the semiconductor substrate.
Dependencies are inferred from the claim text.