Memory circuit including tracking circuit

A method, comprising:

• charging a first node to a first predetermined voltage level, the first node being electrically coupled with a tracking circuit for corresponding memory cells, each of the memory cells including a corresponding storage transistor which has a common predetermined configuration;
• adjusting a variable waiting period of the tracking circuit, the tracking circuit including a first finger circuit which includes (A) a first tracking bit line electrically coupled to the first node and (B) a first set of first tracking cells electrically coupled in series between the first node and a reference voltage node, each first tracking cell including a first shadow transistor corresponding to the common predetermined configuration, the first node having a second predetermined voltage level, gate terminals of the first shadow transistors being coupled with a tracking word line, the adjusting including:
• relative to a first set of tracking cells,
• selectively electrically coupling a second finger circuit between the first node and a second node and in parallel with the first finger circuit;
• discharging the first node toward the second predetermined voltage level during the variable waiting period;
• and
• generating a reset signal based on a signal at the first node.

A memory circuit comprising:

• memory cells arranged in an array, each memory cell including a storage transistor corresponding to a predetermined configuration;
• and
• a tracking circuit including:
• a tracking bit line;
• a tracking word line;
• a first finger circuit coupled between a first node of the tracking bit line and a reference voltage node, the first finger circuit including:
• a first set including a first number quantity of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with the tracking word line;
• and
• a second finger circuit coupled between the first node of the tracking bit line and the reference voltage node, the second finger circuit including:
• a second set including a second number of second tracking cells, each second tracking cell including a second shadow transistor corresponding to the predetermined configuration, gate terminals of the second shadow transistors being coupled with the tracking word line;
• and
• wherein the first number of the first tracking cells in the first set is different than the second number of the second tracking cells in the second set.