Command buffer chip with dual configurations

A buffer chip comprising:

• a first set of input/output (I/O) pins;
• and
• a second set of I/O pins;
• wherein the buffer chip is configurable to operate in one of a first mode or a second mode;
• wherein the first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode;
• and
• wherein the first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between the buffer chip and a non-volatile memory controller coupled to one or more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.