US 11,443,782 B2 · Electronic device to perform read operation and mode register read operation

Abstract

An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

Claims20

Dependent claims

An electronic device comprising:

a column control circuit configured to generate a column control pulse, an internal column control pulse, and a mode register enable signal, each of which includes a pulse that is generated according to the logic levels of a chip selection signal and a command address;
and
a control circuit configured to generate a data output control signal based on the column control pulse and the internal column control pulse according to the logic level of the mode register enable signal and configured to generate a read control signal for a read operation and a mode register control signal for a mode register read operation by delaying a read sum signal that is generated based on any one of the column control pulse and the internal column control pulse.

An electronic device comprising:

a control circuit configured to generate a data output control signal for a read operation based on a column control pulse and an internal column control pulse according to the logic level of a mode register enable signal, configured to generate a read control signal for the read operation and a mode register control signal for a mode register read operation based on any one of the column control pulse and the internal column control pulse, and configured to generate a first input control signal, a second input control signal, a first output control signal, and a second output control signal based on any one of the column control pulse and the internal column control pulse;
and
an input/output circuit configured to output, as data, any one of internal data that is generated through a core circuit and an operation code generated through an operation code generation circuit, according to the logic levels of the read control signal and the mode register control signal.

Dependencies are inferred from the claim text.

Facts

Application

17/306,598Filed 3 May 2021 · continuation in part

Priority

KR 10-2020-00661101 Jun 2020

Published

US 2021/0375336 A12 Dec 2021

Granted

13 Sep 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1018
Read-write modes for single port memories, i.e. having either a random port or a serial port: serial bit line access mode, e.g. using bit line…
G11C 7/1039
Read-write modes for single port memories, i.e. having either a random port or a serial port: using pipelining techniques, i.e. using latches…

Electronic device to perform read operation and mode register read operation

Life of this patent

Electronic device to perform read operation and mode register read operation

Life of this patent

Abstract

Claims20