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US 11,443,780 B2Granted
Vertical access line multiplexor
AssigneeMicron Technology, Inc.
InventorsYuan He, Beau D. Barry, Tae H. Kim, Christopher J. Kawamura
Life of this patent
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Abstract
An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.
Claims17
An apparatus, comprising:
- an access line multiplexor formed under a plurality of vertically stacked tiers of memory cells, the multiplexor comprising:
- a first terminal of a first n-type metal oxide semiconductor (nMOS) transistor coupled to a vertical access line and to a first terminal of a second nMOS transistor;
- a second terminal of the first nMOS transistor coupled to a horizontal access line;
- and
- a second terminal of the second nMOS transistor coupled to a negative power supply;
- wherein the vertical access line is coupled to a plurality of gates of a plurality of memory cells in the vertically stacked tiers;
- wherein the horizontal access line is coupled to a plurality of additional vertical access lines via a plurality of additional multiplexors;
- and
- wherein the apparatus further comprises control circuitry configured to simultaneously:
- cause the multiplexor to electrically couple the vertical access line to the horizontal access line;
- and
- cause the plurality of additional multiplexors to electrically decouple the plurality of additional vertical access lines from the horizontal access line.
9 more elements
A memory device, comprising:
- an array of memory cells comprising:
- a plurality of vertically stacked tiers of memory cells;
- a plurality of vertical access lines coupled to the plurality of tiers;
- and
- a respective plurality horizontal sense lines coupled to each of the plurality of tiers;
- semiconductor under the array circuitry, comprising a plurality of multiplexers, wherein each multiplexor comprises:
- a first terminal of a first transistor coupled to a respective vertical access line and to a first terminal of a second transistor;
- a second terminal of the first transistor coupled to a horizontal access line;
- and
- a second terminal of the second transistor coupled to a negative power supply;
- and
- a plurality of sense amplifiers each coupled to a respective subset of the plurality of horizontal sense lines;
- wherein the respective subset of the plurality of horizontal sense lines comprises one sense line in each of the plurality of tiers;
- and
- wherein the respective subset of the plurality of horizontal sense lines is coupled to the respective sense amplifier via a staircase connection.
12 more elements
A method of sensing a memory cell in an array, comprising:
- among a plurality of vertical access lines physically coupled to each of a plurality of vertically stacked tiers of memory cells and to a horizontal access line:
- electrically coupling a particular vertical access line of the plurality of vertical access lines to the horizontal access line via a particular multiplexer in semiconductor under the array circuitry, wherein the particular vertical access line is coupled to the memory cell;
- electrically decoupling a remainder of the plurality of vertical access lines from the horizontal access line via respective other multiplexors in the semiconductor under the array circuitry;
- activating a horizontal sense line coupled to the memory cell;
- and
- sensing the memory cell with a sense amplifier coupled to the horizontal sense line via a staircase connection, wherein the sense amplifier is horizontally adjacent to the plurality of vertically stacked tiers of memory cells.
3 more elements
Dependencies are inferred from the claim text.