Back to results
US 11,443,777 B2Granted
Backside power rail architecture
AssigneeArm Limited
InventorsAndy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Sony, Ettore Amirante, Ayush Kulshrestha
Life of this patent
Estimating the term…
Abstract
Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.
Claims19
A device, comprising:
- first backside power rails that supply a core voltage to memory logic;
- and
- second backside power rails that supply a periphery voltage to control logic,
- wherein at least one first backside power rail has a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic, and
- wherein the rail break provides a spatial opening in the at least one first backside power rail to allow coupling of the at least one second backside power rail to the control logic.
2 more elements
A device, comprising:
- first backside power rails that supply a core voltage to memory logic;
- second backside power rails that supply a periphery voltage to control logic, wherein at least one first backside power rail has a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic;
- a frontside power distribution network that provides frontside power rails;
- a backside power distribution network that provides the first backside power rails and the second backside power rails disposed underneath the frontside power rails;
- and
- transition cells that provide frontside-to-backside power distribution.
3 more elements
A device, comprising:
- first backside power rails that supply a core voltage to memory logic;
- and
- second backside power rails that supply a periphery voltage to control logic,
- third backside power rails that couple the memory logic and the control logic to ground,
- wherein at least one first backside power rail has multiple rail breaks that interrupt continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic and so as to allow at least one third backside power rail to couple the memory logic and the control logic to ground.
2 more elements
A device, comprising:
- memory circuitry including memory logic and control logic;
- and
- rows of backside power rails having one or more rail breaks that allow multiple different nets to supply power to the memory logic and the control logic,
- wherein alignment of the rail breaks in one or more first regions allow for core voltage in multiple domains to be supplied from different rows of the backside power rails, and
- wherein alignment of the rail breaks in one or more second regions allow for periphery voltage in multiple domains to be supplied from different rows of the backside power rails.
2 more elements
Dependencies are inferred from the claim text.