Memory system design for signal integrity crosstalk reduction with asymmetry
AssigneeQUALCOMM Incorporated
InventorSunil Gupta
Life of this patent
Estimating the term…
Abstract
An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.
Claims12
An integrated circuit, comprising:
- a printed circuit board (PCB);
- a package substrate interconnected on the PCB, the package substrate comprising parallel signal traces arranged in an asymmetric routing;
- a system on chip (SoC) die interconnected on the package substrate, the SOC die comprising a parallel memory interface coupled to the parallel signal traces of the package substrate through package interconnects;
- and
- a memory device package on the SoC die and coupled to the parallel memory interface of the SoC die through the parallel signal traces arranged in the asymmetric routing of the package substrate, in which a variable spacing is provided between the parallel signal traces for a majority portion of the parallel signal traces of a longest leg of an internal signal integrity channel.
An integrated circuit, comprising:
- a package substrate comprising parallel signal traces arranged in an asymmetric routing;
- a die interconnected on the package substrate and having a parallel memory interface coupled to the plurality of parallel signal traces of the package substrate through package interconnects, in which the parallel signal traces of the package substrate are spaced apart based on uneven trace spaces,
- in which a trace space between inner ones of the parallel signal traces is greater than a trace space between outer ones of the parallel signal traces for a majority portion of the parallel signal traces of a longest leg of an internal signal integrity channel;
- and
- a memory device package stacked on the die and coupled to the parallel memory interface of the die through the asymmetric routing of the package substrate.
Dependencies are inferred from the claim text.