Shift register having a compensation circuit, shift register circuit and display device

A shift register circuit, comprising:

• N cascading shift registers, wherein N is an integer greater than one and any one of the N cascading shift registers comprises:
• an input circuit connected to a pull-up node and configured to provide a signal to the pull-up node;
• a compensation circuit connected to the pull-up node and configured to transmit a compensation signal to the pull-up node, the compensation circuit being connected to the input circuit;
• an output circuit connected to the pull-up node, an output end, and a first phase clock signal end, and configured to transmit a signal of the first phase clock signal end to the output end in response to a signal of the pull-up node, the output circuit being connected to the input circuit and the compensation circuit;
• a pull-down control circuit connected to a first signal end, a pull-down control node, a pull-down node, the pull-up node, and a second signal end, and configured to transmit a signal of the second signal end to the pull-down node and the pull-down control node in response to the signal of the pull-up node, and transmit a signal of the first signal end to the pull-down control node and the pull-down node in response to the signal of the first signal end, the pull-down control circuit being connected to the input circuit;
• a pull-down circuit connected to the pull-up node, the pull-down node, the output end, and the second signal end, and configured to transmit the signal of the second signal end to the pull-up node and the output end in response to a signal of the pull-down node, the pull-down circuit being connected between the compensation circuit and the output circuit;
• and
• a reset circuit connected to a reset end, the second signal end, and the pull-up node, and configured to transmit the signal of the second signal end to the pull-up node in response to a signal of the reset end, the reset circuit being connected between the input circuit and the pull-down circuit,
• wherein, according to a cascade relationship of the cascading shift registers, the second signal ends of the cascading shift registers at a first stage to an N-th stage are sequentially connected to N-th signal terminal to first signal terminal.

A display device, comprising:

• a shift register circuit comprising N cascading shift registers, wherein N is an integer greater than one and any one of the N cascading shift registers comprises:
• an input circuit connected to a pull-up node and configured to provide a signal to the pull-up node;
• a compensation circuit connected to the pull-up node and configured to transmit a compensation signal to the pull-up node, the compensation circuit being connected to the input circuit;
• an output circuit connected to the pull-up node, an output end, and a first phase clock signal end, and configured to transmit a signal of the first phase clock signal end to the output end in response to a signal of the pull-up node, the output circuit being connected to the input circuit and the compensation circuit;
• a pull-down control circuit connected to a first signal end, a pull-down control node, a pull-down node, the pull-up node, and a second signal end, and configured to transmit a signal of the second signal end to the pull-down node and the pull-down control node in response to the signal of the pull-up node, and transmit a signal of the first signal end to the pull-down control node and the pull-down node in response to the signal of the first signal end, the pull-down control circuit being connected to the input circuit;
• a pull-down circuit connected to the pull-up node, the pull-down node, the output end, and the second signal end, and configured to transmit the signal of the second signal end to the pull-up node and the output end in response to a signal of the pull-down node, the pull-down circuit being connected between the compensation circuit and the output circuit;
• and
• a reset circuit connected to a reset end, the second signal end, and the pull-up node, and configured to transmit the signal of the second signal end to the pull-up node in response to a signal of the reset end, the reset circuit being connected between the input circuit and the pull-down circuit,
• wherein, according to a cascade relationship of the cascading shift registers, the second signal ends of the cascading shift registers at a first stage to an N-th stage are sequentially connected to N-th signal terminal to first signal terminal.