Data driver and display device including a data driver

A data driver for providing data voltages to a display panel, the data driver comprising:

• a shift register array block which generates sampling signals in response to first, second, third and fourth start signals, first, second, third and fourth direction signals, and first and second clock signals;
• a sampling latch array which samples output image data in response to the sampling signals;
• a holding latch array which stores the output image data sampled by the sampling latch array in response to a load signal;
• a digital-to-analog converter array which converts the output image data output from the holding latch array into the data voltages;
• and
• an output buffer array which outputs the data voltages at output terminals,
• wherein the shift register array block includes:
• a first shift register array which generates a first portion of the sampling signals in response to the first start signal, the first direction signal and the first clock signal;
• a second shift register array which generates a second portion of the sampling signals in response to the second start signal, the second direction signal and the second clock signal;
• a third shift register array which generates a third portion of the sampling signals in response to the third start signal, the third direction signal and the first clock signal;
• and
• a fourth shift register array which generates a fourth portion of the sampling signals in response to the fourth start signal, the fourth direction signal and the second clock signal,
• wherein, in a case where the display panel is a normal display panel, the shift register array block generates the sampling signals in a first order, and
• wherein, in a case where the display panel is a dead space reduced display panel, the shift register arrat block generates the sampling signals in a second order different from the first order.

A display device comprising:

• a display panel;
• a data driver providing data voltages to the display panel;
• and
• a controller which provides output image data to the data driver,
• wherein the data driver includes:
• a shift register array block which generates sampling signals in response to first, second, third and fourth start signals, first, second, third and fourth direction signals and first and second clock signals;
• a sampling latch array which samples output image data in response to the sampling signals;
• a holding latch array which stores the output image data sampled by the sampling latch array in response to a load signal;
• a digital-to-analog converter array which converts the output image data output from the holding latch array into the data voltages;
• and
• an output buffer array which outputs the data voltages at output terminals,
• wherein the shift register array block includes:
• a first shift register array which generates a first portion of the sampling signals in response to the first start signal, the first direction signal and the first clock signal;
• a second shift register array which generates a second portion of the sampling signals in response to the second start signal, the second direction signal and the second clock signal;
• a third shift register array which generates a third portion of the sampling signals in response to the third start signal, the third direction signal and the first clock signal;
• and
• a fourth shift register array which generates a fourth portion of the sampling signals in response to the fourth start signal, the fourth direction signal and the second clock signal,
• wherein the first, second, third and fourth start signals are left odd, left even, right odd and right even start signals, respectively,
• wherein the first, second, third and fourth direction signals are left odd, left even, right odd and right even direction signals, respctively,
• wherein the first and second clock signals are odd and even clock signals, respectively,
• wherein the first shift register array is a left odd shift register array which generates left odd sampling signals as the first portion of the sampling signals in response to the left odd start signal, the left odd direction signal and the odd clock signal,
• wherein the second shift register array is a left even shift register array which generates left even sampling signals as the second portion of the sampling signals in response to the left even start signal, the left even direction signal and the even clock signal,
• wherein the third shift register array is a right odd shift register array which generates right odd sampling signals as the third portion of the sampling signals in response to the right odd start signal, the right odd direction signal and the odd clock signal, and
• wherein the fourth shift register array is a right even shift register array which generates right even sampling signals as the fourth portion of the sampling signals in response to the right even start signal, the right even direction signal and the even clock signal.