Display device, gate drive circuit, shift register including two shift register units and control method thereof

A gate drive circuit comprising a plurality of shift registers which are cascaded,

• wherein each of the plurality of shift registers comprises a first shift register unit and a second shift register unit,
• the first shift register unit is electrically connected with a first node, a first signal input terminal, a first clock signal terminal and a first signal output terminal, the second shift register unit is electrically connected with the first node, a second signal input terminal, a second clock signal terminal and a second signal output terminal,
• the first shift register unit is configured to write a first control signal to the first node under control of a first input signal provided by the first signal input terminal, and write a first clock signal provided by the first clock signal terminal to the first signal output terminal under control of a voltage of the first node;
• the second shift register unit is configured to write a second control signal to the first node under control of a second input signal provided by the second signal input terminal, and write a second clock signal provided by the second clock signal terminal to the second signal output terminal under control of the voltage of the first node;
• any two adjacent frames comprise a first frame and a second frame,
• during time of the first frame, the first clock signal and the first input signal are pulse signals, and the second clock signal and the second input signal are DC signals;
• and
• during time of the second frame, the first clock signal and the first input signal are DC signals, and the second clock signal and the second input signal are pulse signals.

A control method of a shift register,

• wherein the shift register comprises a first shift register unit and a second shift register unit,
• the first shift register unit is electrically connected with a first node, a first signal input terminal, a first clock signal terminal and a first signal output terminal, the second shift register unit is electrically connected with the first node, a second signal input terminal, a second clock signal terminal and a second signal output terminal,
• the first shift register unit is configured to write a first control signal to the first node under control of a first input signal provided by the first signal input terminal, and write a first clock signal provided by the first clock signal terminal to the first signal output terminal under control of a voltage of the first node;
• the second shift register unit is configured to write a second control signal to the first node under control of a second input signal provided by the second signal input terminal, and write a second clock signal provided by the second clock signal terminal to the second signal output terminal under control of the voltage of the first node;
• any two adjacent frames comprise a first frame and a second frame,
• during time of the first frame, the first clock signal and the first input signal are pulse signals, and the second clock signal and the second input signal are DC signals;
• and
• during time of the second frame, the first clock signal and the first input signal are DC signals, and the second clock signal and the second input signal are pulse signals,
• the control method comprises:
• during the time of the first frame, writing the first control signal to the first node through the first shift register unit under control of the first input signal, and writing the first clock signal to the first signal output terminal through the first shift register unit under control of the voltage of the first node, wherein the first clock signal and the first input signal are pulse signals;
• during the time of the second frame, writing the second control signal to the first node through the second shift register unit under control of the second input signal, and writing the second clock signal to the second signal output terminal through the second shift register unit under control of the voltage of the first node, wherein the second clock signal and the second input signal are pulse signals.