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US 11,443,405 B2Granted
Mechanism to accelerate graphics workloads in a multi-core computing architecture
AssigneeIntel IP Corporation
InventorsCarsten Benthin, Sven Woop, Ingo Wald
Life of this patent
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Abstract
A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
Claims20
An apparatus comprising:
- a processor including a plurality of processor cores, the processor including:
- a first processor core to process a first plurality of threads;
- a second processor core to process a second plurality of threads;
- and
- a first cache memory coupled to the first processor core and the second processor core;
- a first field programmable gate array (FPGA) coupled to the first processor core, the first FPGA to accelerate execution of workloads processed at the first processor core;
- a second FPGA coupled to the second processor core, the second FPGA to accelerate execution of workloads processed at the second processor core;
- and
- a second cache memory coupled with and shared between the first processor core, second processor core, and the first FPGA, wherein the first FPGA is an independent agent to the second cache memory.
6 more elements
A method comprising:
- processing a first plurality of threads via a first processor core of a processor including a plurality of processor cores;
- processing a second plurality of threads via a second processor core of the processor;
- while processing the first plurality of threads and the second plurality of threads, reading data from a cache memory coupled with the first processor core and the second processor core;
- accelerating a first workload processed by the first plurality of threads via a first field programmable gate array (FPGA) coupled to the first processor core, wherein the first FPGA is to accelerate execution of workloads processed at the first processor core and is an independent agent to a second cache memory shared between the first processor core, second processor core, and first FPGA;
- and
- accelerating a second workload processed by the second plurality of threads via a second FPGA coupled to the second processor core, wherein the second FPGA is to accelerate execution of workloads processed at the second processor core.
3 more elements
A data processing system comprising:
- a peripheral bus interconnect;
- and
- a processor coupled with the peripheral bus interconnect, the processor including:
- a first processor core to process a first plurality of threads;
- a second processor core to process a second plurality of threads;
- and
- a cache memory coupled to the first processor core and the second processor core;
- a first field programmable gate array (FPGA) coupled to the first processor core, the first FPGA to accelerate execution of workloads processed at the first processor core, wherein the first processor core is to select a first workload to be accelerated at the first FPGA;
- a second FPGA coupled to the second processor core, the second FPGA to accelerate execution of workloads processed at the second processor core, wherein the second processor core is to select a second workload to be accelerated at the second FPGA;
- and
- a second cache memory coupled with and shared between the first processor core, second processor core, and the first FPGA, wherein the first FPGA is an independent agent to the second cache memory.
8 more elements
Dependencies are inferred from the claim text.