Synapse array of neuromorphic device including synapses having ferro-electric field effect transistors and operation method of the same

A synapse array of a neuromorphic device comprising:

• a plurality of pre-synaptic neurons;
• a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
• a plurality of post-synaptic neurons;
• a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction;
• and
• a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
• wherein each of the plurality of synapses comprises:
• an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET;
• and
• a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
• wherein
• each of the plurality of row lines comprises a first synaptic row line and a second synaptic row line extending from a pre-synaptic neuron in parallel with each other,
• each of the first synaptic row lines is electrically connected to the drain electrode of the n-FeFET to provide a fixed power supply voltage to the drain electrode of the n-FeFET,
• each of the second synaptic row lines is electrically connected to the drain electrode of the p-FeFET to provide a fixed ground voltage to the drain electrode of the p-FeFET, and
• the resistive element is a fixed resistor having a fixed resistance.

A synapse array of a neuromorphic device comprising:

• a plurality of pre-synaptic neurons;
• a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction, and each row line including a first synaptic row line, a second synaptic row line, and a third synaptic row line extending in parallel with each other;
• a plurality of post-synaptic neurons;
• a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction;
• and
• a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
• wherein each of the plurality of synapses comprises:
• an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• an input port electrically connected in common to the third synaptic row line, the gate electrode of the n-FeFET and the gate electrode of the p-FeFET;
• and
• a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
• wherein
• each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
• each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET
• each of the third synaptic row lines is electrically connected to the gate electrode of each of the n-FeFET and the p-FeFET, and
• the resistive element is a fixed resistor having a fixed resistance.

A method of operating a neuromorphic device comprising:

• setting a first polarization voltage and a second polarization voltage of the neuromorphic device, wherein the first polarization voltage is greater than the second polarization voltage, and
• applying a read voltage to the neuromorphic device to enable current flow, wherein the neuromorphic device comprises:
• a pre-synaptic neuron;
• a row line extending from the pre-synaptic neuron in a row direction;
• a post synaptic neuron;
• a column line extending from the post-synaptic neuron in a column direction;
• and
• a synapse disposed at an intersection region between the row line and the column line,
• wherein the synapse comprises
• an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• an input port electrically connected in common with the row line, the gate electrode of the n-FeFET, and the gate electrode of the p-FeFET;
• and
• a resistive element having two nodes, a first node electrically connected in common to the source electrodes of the n-FeFET and the p-FeFET and a second node electrically connected to the column line, and
• wherein the resistive element is a fixed resistor having a fixed resistance,
• the drain electrode of the n-FeFET is electrically connected to a power supply node to provide a fixed power supply voltage,
• the drain electrode of the p-FeFET is electrically connected to a ground voltage node to provide a fixed ground voltage,
• the first polarization voltage polarizes the gate electrode of the n-FeFET,
• the second polarization voltage polarizes the gate electrode of the p-FeFET, and
• the read voltage is applied to the input port.

A method of operating a neuromorphic device comprising:

• setting a first polarization voltage and a second polarization voltage of the neuromorphic device,
• wherein the first polarization voltage is greater than the second polarization voltage, and applying a read voltage to the neuromorphic device to enable current flow,
• wherein the neuromorphic device comprises:
• a plurality of pre-synaptic neurons;
• a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
• a plurality of post-synaptic neurons;
• a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction;
• and
• a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
• wherein each of the plurality of synapses comprises:
• an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET;
• and
• a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
• wherein
• each of the plurality of row lines includes a first synaptic row line, a second synaptic row line, and a third synaptic row line extending from the plurality of pre-synaptic neurons in parallel with each other,
• each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
• each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET,
• each of the third synaptic row lines is electrically connected to the gate electrode of each of the n-FeFET and the gate electrode of each of the p-FeFET,
• the resistive element is a fixed resistor having a fixed resistance,
• the first polarization voltage polarizes the gate electrode of the n-FeFET,
• the second polarization voltage polarizes the gate electrode of the p-FeFET, and
• the read voltage is applied to the input port.

A method of operating a neuromorphic device comprising:

• setting a first polarization voltage and a second polarization voltage of the neuromorphic device, wherein the second polarization voltage is greater than the first polarization voltage, and
• applying a read voltage to the neuromorphic device to enable current flow,
• wherein the neuromorphic device comprises:
• a plurality of pre-synaptic neurons;
• a plurality of row lines extending from each of the plurality of pre-synaptic neurons in a row direction;
• a plurality of post-synaptic neurons;
• a plurality of column lines extending from each of the plurality of post-synaptic neurons in a column direction;
• and
• a plurality of synapses, each disposed at an intersection region between one of the plurality of row lines and one of the plurality of column lines;
• wherein each of the plurality of synapses comprises:
• an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a drain electrode, a gate electrode, and a body;
• an input port electrically connected in common to the gate electrode of the n-FeFET and the gate electrode of the p-FeFET;
• and
• a resistive element having two nodes, a first node electrically connected in common to the source electrode of the n-FeFET and the source electrode of the p-FeFET, and a second node electrically connected to one of the plurality of column lines,
• wherein
• each of the plurality of row lines includes a first synaptic row line, a second synaptic row line, and a third synaptic row line extending from the plurality of pre-synaptic neurons in parallel with each other,
• each of the first synaptic row lines provides a fixed power supply voltage to the drain electrode of the n-FeFET,
• each of the second synaptic row lines provides a fixed ground voltage to the drain electrode of the p-FeFET,
• each of the third synaptic row lines is electrically connected to the gate electrode of each the n-FeFET and the gate electrode of each the p-FeFET,
• the resistive element is a fixed resistor having a fixed resistance,
• the first polarization voltage polarizes the gate electrode of the n-FeFET,
• the second polarization voltage polarizes the gate electrode of the p-FeFET, and
• the read voltage is applied to the input port.