Back to results
US 11,443,096 B2Granted
Method for optimizing floor plan for an integrated circuit
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc Nanjing Company, Limited
InventorsYi-Lin Chuang, Shi-Wen Tan, Song Liu, Shih-Yao Lin, Wen-Yuan Fang
Life of this patent
Estimating the term…
Abstract
A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.
Claims20
A method, comprising:
- generating a floor plan having a plurality of macros for an integrated circuit;
- adjusting the plurality of macros according to a channel area interposed between a plurality of pins;
- separating the plurality of macros by a channel width of the channel area;
- and
- adjusting, in accordance with correlations between the plurality of macros and a plurality of registers, the plurality of macros in the floor plan.
2 more elements
A system, comprising:
- one or more processing units;
- and
- a memory unit configured to store instructions that when executed by at least one of the one or more processing units perform operations, comprising:
- place a plurality of macros around a centroid of a region in a floor plan according to a plurality of weights of the plurality of macros;
- adjust a plurality of pins of the plurality of macros to face each other;
- predict a channel width for each of a plurality of channels interposed between the plurality of macros;
- adjust the plurality of macros according to the channel width of each of the plurality of channels;
- detect correlations between the plurality of macros and a plurality of registers;
- and
- adjust the plurality of macros according to the correlations.
7 more elements
A method, comprising:
- placing, in accordance with a plurality of weights of a plurality of macros, a first portion of the plurality of macros closer to a centroid of a core region in a floor plan of an integrated circuit than a second portion of the plurality of macros;
- and
- separating the plurality of macros by a plurality of channels, wherein the plurality of macros have a plurality of pins coupled to the plurality of channels interposed between the plurality of macros.
Dependencies are inferred from the claim text.