Hotspot avoidance method for manufacturing integrated circuits

A method comprising:

• cropping a plurality of images from a layout of an integrated circuit, wherein the cropping comprises:
• dividing the layout of the integrated circuit into an array of rectangular regions, each being one of the plurality of images;
• generating a plurality of hash values, each from one of the array of rectangular regions;
• searching from a hotspot library to find similar hash values that are similar to the plurality of hash values, wherein the hotspot library stores hash values indexed to images that have hotspots;
• and
• marking positions of some of the plurality of images that are associated with the similar hash values on the layout of the integrated circuit.

A method comprising:

• finding a hotspot from a layout image of an integrated circuit;
• searching for a polishing recipe from a library stored in a tangible media, the library comprising an entry, and the entry comprising:
• a hash value, wherein the hash value comprises a series of digits and letters;
• an image associated with the hash value, wherein the image comprises the hotspot;
• the polishing recipe configured to reduce the hotspot;
• and
• a topology information of the hotspot;
• and
• using the polishing recipe to perform a polishing process on a wafer, wherein the wafer comprises the integrated circuit formed therein.