Method of inserting dummy boundary cells for macro/IP and IC
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Yi Hu, Chih-Ming Chao, Chi-Yeh Yu
Estimating the term…
Methods for inserting dummy boundary cells in an integrated circuit (IC) are provided. A plurality of macros and a top channel are merged into floorplan of the IC. The top channel is arranged between the macros and is filled with a plurality of first dummy boundary cells, and each of the macros includes a macro boundary and a main pattern surrounded by the macro boundary. The first dummy boundary cells within the top channel and between a first macro and a second macro are replaced with a plurality of second dummy boundary cells. The macro boundaries of the first and second macros are formed by the second dummy boundary cells. First gate length of dummy patterns within the first dummy boundary cells is greater than second gate length of dummy patterns within the second dummy boundary cells. The first and second dummy boundary cells are the same size.
A method for inserting dummy boundary cells in an integrated circuit (IC), comprising:
A method for inserting dummy boundary cells in an integrated circuit (IC), comprising:
A method for inserting dummy boundary cells in an integrated circuit (IC), comprising:
Dependencies are inferred from the claim text.