Data processing engines with cascade connected cores

An integrated circuit, comprising:

• a plurality of data processing engines (DPEs) each including a core configured to perform computations;
• wherein a first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core, wherein the input cascade connection is coupled to a plurality of source cores of the plurality of DPEs;
• wherein the input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is coupled to a cascade output of a different one of the plurality of source cores;
• wherein the input cascade connection is programmable to enable a selected one of the plurality of inputs;
• wherein the first DPE includes an output cascade connection coupled to a cascade output of the first core and to each of a plurality of target cores of the plurality of DPEs;
• and
• wherein the output cascade connection includes a plurality of outputs, wherein each of the plurality of outputs is coupled to a cascade input of a different one of the plurality of target cores.