Timing verification of non-standard library blocks

A method comprising:

• identifying a signal path in an integrated circuit design, the signal path including a driver circuit, an interconnect, and a receiver circuit;
• generating a substitute integrated circuit design by:
• replacing the driver circuit of the signal path with a primitive standard library cell;
• providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool;
• and
• replacing the receiver circuit with one or more capacitors;
• and
• executing the static timing analysis tool on the substitute integrated circuit design to determine whether a propagation delay from the driver circuit to the receiver circuit of the signal path satisfies a timing requirement of the integrated circuit design.

A non-transitory computer-readable medium storing code which, when executed by one or more processors, causes the one or more processors to perform operations including:

• identifying a signal path in an integrated circuit design, the signal path including a driver circuit, an interconnect, and a receiver circuit;
• generating a substitute integrated circuit design by:
• replacing the driver circuit of the signal path with a primitive standard library cell of a standard library having a closest drive strength as the driver circuit;
• providing parasitic parameters of the interconnect in a format compatible with a static timing analysis tool;
• and
• replacing a transistor of the receiver circuit with a capacitor having an equivalent capacitance;
• and
• executing the static timing analysis tool on the substitute integrated circuit design to determine whether the signal path contains a timing violation.