US 11,443,087 B2 · System and method for power analysis for design logic circuit with irregular clock

Abstract

A system is disclosed that includes a memory and a processor configured to perform operations stored in the memory. The processor performs the operations to select a master clock for a plurality of clocks in a design logic circuit. The processor further performs the operations to align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock. The aligned clock edge of the clock limits a number of emulation cycles for the design logic to a fixed number of emulation cycles required for the master clock The processor further performs the operation to determine a clock period for measuring power required for the design logic circuit and estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period, which corresponds to a clock selected from the plurality of clocks and the master clock.

Claims20

Dependent claims

A system, comprising:

a memory;
and
a processor configured to perform operations stored in the memory, wherein the processor executes the operations to:
select a master clock for a plurality of clocks in a design logic circuit, wherein the master clock is a least-gated clock in the design logic circuit;
align a clock edge of a clock of the plurality of clocks with a corresponding nearest clock transition of the master clock;
determine a clock period for measuring power required for the design logic circuit;
and
estimate, at the aligned clock edge, the power required for the design logic circuit corresponding to the determined clock period.

5 more elements

Dependencies are inferred from the claim text.

System and method for power analysis for design logic circuit with irregular clock

Life of this patent

System and method for power analysis for design logic circuit with irregular clock

Life of this patent

Abstract

Claims20