Techniques for preventing voltage tampering of security control circuits

A method for preventing voltage tampering of a security control circuit in an integrated circuit, the method comprising:

• comparing a supply voltage to a threshold voltage with a comparator circuit to generate a control signal;
• providing a clock signal generated by a clock signal generation circuit to a clock input of a first timing circuit in the security control circuit;
• providing supply current from the supply voltage to the first timing circuit;
• decreasing a frequency of the clock signal to a reduced frequency with the clock signal generation circuit in response to the control signal indicating that the supply voltage has decreased below the threshold voltage;
• performing a security function for the integrated circuit with the security control circuit;
• and
• storing data associated with the security function in the first timing circuit in response to the clock signal with the reduced frequency without causing a timing violation in the first timing circuit.

An integrated circuit comprising:

• a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage;
• an input buffer circuit coupled to an input/output pad of the integrated circuit;
• a first control circuit that blocks signal transmission from the input/output pad to the input buffer circuit in response to the control signal indicating that the supply voltage is less than the threshold voltage;
• an output buffer circuit coupled to the input/output pad;
• and
• a second control circuit that blocks signal transmission from the output buffer circuit to the input/output pad in response to the control signal indicating that the supply voltage is less than the threshold voltage.