Secure debug architecture
AssigneeSiFive, Inc.
InventorsYann Loisel, Frank Lhermet
Life of this patent
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AssigneeSiFive, Inc.
InventorsYann Loisel, Frank Lhermet
Estimating the term…
Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.
An integrated circuit for executing instructions comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.