Targeted very long delay for increasing speculative execution progression

A system comprising:

• a processor,
• memory coupled to the processor, the memory having stored therein instructions that when executed cause the processor to:
• receive a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory location following the first load instruction, wherein the speculative memory access instruction is dependent, either directly or indirectly, on information returned by the first load instruction from the first memory location;
• execute the first load instruction from the first memory location and delaying a return of data from the first memory location for a number of processor cycles;
• and
• during the delay in returning data from the first memory location, speculatively execute additional instructions in the test scenario, the speculatively executing comprising:
• executing the speculative memory access instruction from the second memory location.

A computer program product for advancing speculative execution in microarchitectures, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• receive a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory location following the first load instruction, wherein the speculative memory access instruction is dependent, either directly or indirectly, on information returned by the first load instruction from the first memory location;
• execute the first load instruction from the first memory location and delaying a return of data from the first memory location for a number of processor cycles;
• and
• during the delay in returning data from the first memory location, speculatively execute additional instructions in the test scenario, the speculatively executing comprising:
• executing the speculative memory access instruction from the second memory location.