MAC processing pipelines, circuitry to control and configure same, and methods of operating same
AssigneeFlex Logix Technologies, Inc.
InventorsFrederick A. Ware, Cheng C. Wang
Life of this patent
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AssigneeFlex Logix Technologies, Inc.
InventorsFrederick A. Ware, Cheng C. Wang
Estimating the term…
An integrated circuit including control/configure circuitry which interfaces with a plurality of interconnected (e.g., serially) multiplier-accumulator circuits and/or one or more rows of interconnected (e.g., serially) multiplier-accumulator circuits. The control/configure circuitry may include a plurality of control/configure circuits, each control/configure circuit interfaces with at least one multi-bit MAC execution pipeline, wherein each pipeline includes a plurality of interconnected (e.g., serially) multiplier-accumulator circuits. Each control/configure circuit may include one or more (or all) of (i) a configurable input data signal path to provide data to the MACs of the pipeline during the execution sequence(s), (ii) a configurable accumulation data path for the ongoing/accumulating MAC accumulation totals generated by the MACs during an execution sequence, and (iii) a configurable output data path for the output data generated by execution sequence (i.e., input data that was processed via the multiplier-accumulator circuits or MAC processors of the execution pipeline).
An integrated circuit comprising:
An integrated circuit comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.