Memory sequencer system and a method of memory sequencing using thereof

A memory sequencer system for external memory protocols, the memory sequencer system comprising:

• a control center including a microcontroller;
• a control center network-on-chip including nodes interconnected to synchronize and co-ordinate communications;
• a command and address sequencer to generate commands and addresses, and control the commands based on the respective addresses for specific memory protocols;
• and
• at least one data sequencer to generate pseudo-random or deterministic data patterns for each byte lane of a memory interface, wherein
• said command and address sequencer and said data sequencer are chained to form complex address and data sequences for memory interface training, calibrating and debugging;
• said control center network-on-chip interconnecting the control center with said command and address sequencer and data sequencer;
• wherein said command and address sequencer includes a command sequence table to interpret each entry by cycling through said table to orchestrate command, address or data sequence generation;
• and
• wherein said address sequencer includes a set of adders or comparators to trigger incrementing of a different adder or comparator set within the same set based on a trigger value.