Arbitration control for pseudostatic random access memory device

An arbitration control circuit in a pseudo-static random access memory (PSRAM) device, the arbitration control circuit comprising:

• a set-reset (SR) latch circuit receiving a first input signal being a normal access request signal indicative of a read or write access request to memory cells of the PSRAM device, and a second input signal being a refresh access request signal indicative of a refresh access request to memory cells of the PSRAM device, the SR latch circuit generating a first output signal in response to a logical operation of the first input signal and the second input signal, the first output signal having no signal transition in response to the first input signal being asserted before the second input signal being asserted, or having two or more signal transitions in response to the first input signal being asserted after or simultaneously with the second input signal being asserted;
• a unidirectional delay circuit having an input terminal receiving the first output signal and introducing a first delay to a leading signal transition of the first output signal to generate a delayed signal on an output terminal, the delayed signal having no signal transition in response to the first output signal having no signal transition or having a pulse width shorter than the first delay;
• and
• a D-flip-flop circuit having a data input terminal receiving the first output signal, a clock input terminal receiving the delayed signal, a reset input terminal receiving a reset signal, and an output terminal providing a second output signal, the second output signal having a first logical state in response to the delayed signal having no signal transition and having a second logical state in response to a signal transition in the delayed signal, the second output signal remaining in the second logical state until the reset signal is asserted to reset the second output signal to the first logical state,
• wherein the second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.