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US 11,442,872 B2Granted
Memory refresh operations using reduced power
AssigneeMicron Technology, Inc.
InventorHarish N. Venkata
Life of this patent
Estimating the term…
Abstract
Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.
Claims20
A device, comprising:
- a plurality of memory banks comprising a first memory bank and a second memory bank, wherein each memory bank comprises a plurality of memory circuitries and is configured to store information;
- and
- first sub-bank logic circuitry communicatively coupled to the first memory bank and the second memory bank via a plurality of multiplexers, wherein the first sub-bank logic circuitry is configured to couple to the first memory bank via the plurality of multiplexers and via a plurality of couplings that bypass the plurality of multiplexers, and wherein the first sub-bank logic circuitry transmits a control signal to refresh the second memory bank and the first memory bank when the plurality of multiplexers is operated to permit sharing of the control signal between the first memory bank and the second memory bank.
A method, comprising:
- performing, via a first bank logic circuitry, a memory operation;
- receiving, via the first bank logic circuitry, an indication to initiate a refresh operation;
- receiving, via the first bank logic circuitry, an indication to operate in a reduced-power operation;
- transmitting, via the first bank logic circuitry, a refresh control signal to buffer circuitry coupled to a multiplexer to initiate a reduced-power refresh operation, wherein the multiplexer is coupled between the first bank logic circuitry, a second bank logic circuitry, and a memory bank, wherein the reduced-power refresh operation enables power supplied to the second bank logic circuitry to be reduced while a refresh of the memory bank occurs.
1 more element
A system, comprising:
- a memory controller;
- and
- a memory module communicatively coupled to the memory controller, wherein the memory module comprises:
- first bank logic circuitry coupled to a first memory bank;
- second bank logic circuitry configured to be coupled to a second memory bank and powered-off while the second memory bank is refreshed;
- and
- a switching circuit configured to couple the first bank logic circuitry to the second memory bank instead of the second bank logic circuitry during memory refresh operations in response to a control signal from the memory controller.
4 more elements
Dependencies are inferred from the claim text.