Information processing apparatus having an integrated circuit chip with first and second communication units having address translation function

An information processing apparatus that includes a plurality of integrated circuit (IC) chips which are connected in series,

• wherein at least one target IC chip of the plurality of IC chips comprises:
• a memory space accessible accessed at a first address width;
• a CPU configured to perform processing in a range which is in the memory space and is accessible at a second address width smaller than the first address width;
• a first communication unit, having an address translation function, for performing communication with one IC chip of the plurality of IC chips which are connected in series;
• and
• a second communication unit, having the address translation function, for performing communication with an IC chip in an opposite direction to the one IC chip,
• wherein a first area for accessing the one IC chip via the first communication unit and a second area for accessing the IC chip in the opposite direction via the second communication unit are included in the memory space,
• the CPU included in the target IC chip accesses one of the first communication unit and the second communication unit by using the range which is in the memory space and is accessible at the second address width,
• in a case in which the CPU accesses the first communication unit, a first address value used to access the first communication unit by the address translation function of the first communication unit is translated into a second address value which corresponds to the first area of the memory space of the first address width,
• an access to the one IC chip specified by the second address value is executed
• in a case in which the CPU accesses the second communication unit, a third address value used to access the second communication unit by the address translation function of the second communication unit is translated into a fourth address value which corresponds to the second area of the memory space of the first address width, and
• an access to an IC chip in the opposite direction specified by the fourth address value is executed.

An information processing apparatus that includes a plurality of integrated circuit (IC) chips which are connected in series,

• wherein at least one target IC chip of the plurality of IC chips comprises:
• a memory space accessible at a first address width;
• a CPU configured to perform processing in a range which is in the memory space and is accessible at a second address width smaller than the first address width;
• a first communication unit, having an address translation function, for performing communication with one IC chip of the plurality of IC chips which are connected in series;
• and
• a second communication unit, having the address translation function, for performing communication with an IC chip in an opposite direction to the one IC chip,
• wherein a first area for accessing the one IC chip via the first communication unit and a second area for accessing an IC chip in the opposite direction via the second communication unit are included in the memory space,
• the CPU included in the target IC chip accesses one of the first communication unit and the second communication unit by using the range which is in the memory space and is accessible at the second address width,
• in a case in which the first communication unit included in the target IC chip accepts an access from the one IC chip based on a specified address value in the first area and the specified address value is included in a predetermined range, the access from the one IC chip is processed as an access to the target IC chip,
• in a case in which the first communication unit included in the target IC chip accepts the access from the one IC chip based on the specified address value in the first area and the specified address value is not included in the predetermined range, the access accepted by the first communication unit is transferred to the second communication unit,
• in a case in which the second communication unit included in the target IC chip accepts an access from the IC chip in the opposite direction based on a specified address value in the second area and the specified address value is included in a predetermined range, the access from the IC chip in the opposite direction is processed as an access to the target IC chip, and
• in a case in which the second communication unit included in the target IC chip accepts the access from the IC chip in the opposite direction based on the specified address value in the second area and the specified address value is not included in the predetermined range, the access accepted by the second communication unit is transferred to the first communication unit.