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US 11,442,868 B2Granted
Aggressive write flush scheme for a victim cache
AssigneeTexas Instruments Incorporated
InventorsNaveen Bhoria, Timothy David Anderson, Pete Hippleheuser
Life of this patent
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Abstract
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.
Claims20
A caching system comprising:
- a first sub-cache;
- and
- a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes:
- a set of cache lines;
- line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data;
- and
- an eviction controller configured to:
- determine that a first cache line of the second sub-cache storing write-miss data is full;
- and
- evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
7 more elements
A method for caching data, comprising:
- receiving, by a caching system, a write memory request for a memory address;
- determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache;
- determining, by a second sub-cache of the caching system, that the memory address is not cached in the second sub-cache;
- responsive to determining that the memory address is not cached in the second sub-cache, storing data associated with the write memory request in a first cache line of the second sub-cache;
- responsive to determining that the memory address is not cached in the second sub-cache, storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss;
- determining that the first cache line is full;
- and
- evicting write-miss data stored in the first cache line in response to determining that the first cache line is full.
5 more elements
A device comprising:
- a processor;
- a first sub-cache;
- and
- a second sub-cache in parallel with the first sub-cache;
- wherein the second sub-cache includes:
- a set of cache lines;
- line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and
- an eviction controller configured to:
- determine that a first cache line of the second sub-cache storing write-miss data is full;
- and
- evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.
8 more elements
Dependencies are inferred from the claim text.