Balancing memory-portion accesses
AssigneeMicron Technology, Inc.
InventorDavid Andrew Roberts
Life of this patent
Estimating the term…
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AssigneeMicron Technology, Inc.
InventorDavid Andrew Roberts
Estimating the term…
Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.
An apparatus comprising:
A method comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.