Processing-in-memory and method and apparatus with memory access

A memory access apparatus, comprising:

• a processing-in-memory comprising an internal processor, a memory, and a register;
• a memory controller;
• an external processor;
• and
• a memory management unit (MMU),
• wherein the external processor is configured to transmit offset information to the processing-in-memory, transmit an instruction to the memory controller, and transmit a reference virtual address to the MMU,
• wherein the MMU is configured to convert the reference virtual address into a reference physical address of the memory, and transmit the reference physical address to the memory controller,
• wherein the register is configured to store the transmitted offset information, and
• wherein the internal processor is configured to:
• receive the instruction and the reference physical address from the memory controller,
• determine an offset physical address of the memory based on the offset information,
• determine a target physical address of the memory based on the reference physical address and the offset physical address, and
• perform the instruction by accessing the target physical address.

A memory access method of a processing-in-memory, the method comprising:

• receiving, by an internal processor, an instruction and a reference physical address of a memory from a memory controller;
• determining, by the internal processor, an offset physical address of the memory based on offset information stored in a register;
• determining, by the internal processor, a target physical address of the memory based on the reference physical address and the offset physical address;
• and
• performing, by the internal processor, the instruction by accessing the target physical address.

A memory access method of a processing apparatus, the method comprising:

• transmitting, by an external processor, offset information to a processing-in-memory, transmitting an instruction to a memory controller, and transmitting a reference virtual address to a memory management unit (MMU);
• converting, by the MMU, the reference virtual address into a reference physical address of a memory, and transmitting, by the MMU, the reference physical address to the memory controller;
• storing, by a register, the offset information;
• receiving, by an internal processor, the instruction and the reference physical address from the memory controller;
• determining, by the internal processor, an offset physical address of the memory based on the offset information;
• determining, by the internal processor, a target physical address of the memory based on the reference physical address and the offset physical address;
• and
• performing, by the internal processor, the instruction by accessing the target physical address.