Memory and operation method of memory

A method for operating a memory, comprising:

• receiving N data groups each of which includes K-bit data, where K and N are positive integers;
• generating an M-bit error correction code by using the N data groups as a message, where M is a positive integer;
• and
• storing the N data groups and the M-bit error correction code in N+1 cell regions of a memory core,
• wherein the M-bit error correction code is generated based on a message for an M×[(K*N)+M] check matrix,
• wherein the message of the M×[(K*N)+M] check matrix includes N group indicators distinguishing the N groups, and N parts of bit indicators each of which distinguishes the K-bit data groups in a corresponding one of the N data groups, and
• wherein a hamming distance between the N group indicators respectively corresponding to neighboring data groups among the N group indicators is 1 or M/2.

A memory, comprising:

• an error correction code generation circuit configured to generate an 8-bit error correction code based on a message including 8 data groups each of which includes 16-bit data;
• a memory core including 9 cell regions for storing the 8 data groups and the 8-bit error correction code;
• and
• an error correction circuit configured to correct errors of the 8 data groups that are read from the memory core based on the 8-bit error correction code that is read from the memory core,
• wherein the error correction code generation circuit generates the 8-bit error correction code based on a message for an 8×136 check matrix,
• wherein the message of the 8×136 check matrix includes 8 group indicators distinguishing the 8 data groups, and 8 parts of bit indicators each of which distinguishes the 16-bit data in a corresponding one of the 8 data groups, and
• wherein a hamming distance between the 8 group indicators respectively corresponding to neighboring data groups among the 8 group indicators is 1 or 4.

A memory, comprising:

• an error correction code generation circuit configured to generate an M-bit error correction code based on a message including N data groups each of which includes K-bit data, where K, N and M are positive integers;
• a memory core including N+1 cell regions for storing the N data groups and the M-bit error correction code;
• and
• an error correction circuit configured to correct errors of the N data groups that are read from the memory core based on the M-bit error correction code that is read from the memory core,
• wherein the error correction code generation circuit generates the M-bit error correction code based on a message for an M×[(K*N)+M] check matrix,
• wherein the message part of the M×[(K*N)+M] check matrix includes N group indicators distinguishing the N data groups, and N parts of bit indicators each of which distinguishes the K-bit data in a corresponding one of the N data groups, and
• wherein a sum of the N group indicators respectively corresponding to neighboring data groups among the N group indicators is different from any of the N group indicators.