Watchdog circuit systems

A vehicle electronics device, comprising:

• a windowed watchdog circuit system, comprising:
• a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold time;
• a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorter than the fast threshold time,
• wherein the windowed watchdog circuit system is configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively.

A fast timer system for a circuit, comprising:

• a fast timer module configured to output a first module state and to output a second module state for a fast threshold time after receiving a watchdog strobe signal from the processor;
• a latch having a state input, a clock input, and a latch output, wherein the state input of the latch is operatively connected to the fast timer module to receive the second module state, wherein the clock input is configured to be connected to the processor to receive the watchdog strobe signals, wherein the latch is configured to switch from a first output state indicating that watchdog strobe signal gap time is equal to or longer than the fast time threshold to a second output state indicating the gap time is shorter than the fast time threshold when the state input is receiving the second module state and the clock input receives a watchdog strobe signal;
• and
• a delay module configured to add a predetermined time delay to the first module state and/or the second module state from the fast timer module such that the state input of the latch receives the first and/or second module state from the fast timer module delayed from the watchdog strobe signal received by the clock input.