Bit-packed array processing using SIMD

A method for processing a bit-packed array, comprising:

• determining, by one or more processors, a data element size of the bit-packed array;
• determining, by the one or more processors, a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, wherein the lane configuration is determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane;
• configuring, by one or more processors, the SIMD unit according to the determined lane configuration;
• and
• loading, by one or more processors, one or more data elements into each vector register lane of the SIMD unit,
• wherein loading one or more data elements into each vector register lane is repeated until the determined data element size exceeds a remaining space of each vector register lane.

A system for processing a bit-packed array, comprising:

• memory for storing instructions;
• one or more processors coupled to the memory and configured to execute the stored instructions to:
• determine a data element size of the bit-packed array;
• determine a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, wherein the lane configuration is determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane;
• configure the SIMD unit according to the determined lane configuration;
• and
• load one or more data elements into each vector register lane of the SIMD unit,
• wherein the one or more processors are configured to determine the lane configuration of the SIMD unit according to a lookup table correlating a plurality of different data element sizes with corresponding lane configurations.

A system for processing a bit-packed array, comprising:

• memory for storing instructions;
• one or more processors coupled to the memory and configured to execute the stored instructions to:
• determine a data element size of the bit-packed array;
• determine a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, wherein the lane configuration is determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane;
• configure the SIMD unit according to the determined lane configuration;
• and
• load one or more data elements into each vector register lane of the SIMD unit,
• wherein the one or more processors are configured to repeatedly load one or more data elements into each vector register lane until the determined data element size exceeds a remaining space of each vector register lane.