US 11,442,495 B2 · Separate clocking for components of a graphics processing unit

Abstract

Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

Claims20

Dependent claims

A method comprising:

independently adjusting at least one of a first frequency of a first clock signal received by one or more shader engine modules and a second frequency of a second clock signal received by one or more non-shader-engine modules of a graphics processing unit based on a quantity of events associated with a first workload of the one or more shader engine modules and a quantity of events associated with a second workload of the one or more non-shader-engine modules.

A graphics processing unit (GPU) comprising:

a plurality of dividers;
a plurality of shader engine modules configured to receive first clock signals, each having a first frequency, from a first subset of the plurality of dividers;
a plurality of non-shader-engine modules configured to receive second clock signal signals, each having a second frequency, from a second subset of the plurality of dividers;
and
a controller configured to output a first control signal to the first subset of the plurality of dividers to selectively control the first frequency of the first clock signals and to output a second control signal to the second subset of the plurality of dividers to selectively control the second frequency of the second clock signals based on a quantity of events associated with a first detected workload of the plurality of shader engine modules and a quantity of events associated with a second detected workload of the plurality of non-shader-engine modules.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/032,701Filed 25 Sep 2020 · us provisional application

Priority

6 Mar 2020

Published

US 2021/0278873 A19 Sep 2021

Granted

13 Sep 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
G06F 1/3228
Monitoring of events, devices or parameters that trigger a change in power modality: monitoring task completion, e.g. by use of idle timers, stop…

Separate clocking for components of a graphics processing unit

Life of this patent

Separate clocking for components of a graphics processing unit

Life of this patent

Abstract

Claims20