Dynamic power monitor monitoring power basted on clock cycle, processor, and system on chip

A processor comprising:

• a plurality of cores, each of which comprises an internal logic circuit and a dynamic power monitor circuit, the internal logic circuit being configured to operate based on an operating voltage and a clock signal, and the dynamic power monitor circuit being configured to monitor power by using state values of internal signals of the internal logic circuit according to cycles of the clock signal to obtain filtered values of the power classification values of the cores and identify transition values based on difference values between the filtered values to obtain a monitoring result;
• an output control circuit configured to generate a trigger signal based on the monitoring result obtained by the dynamic power monitor circuit of each of the plurality of cores;
• a clock manager circuit configured to scale the clock signal provided to the plurality of cores based on the trigger signal;
• and
• an internal voltage regulator configured to scale the operating voltage provided to the plurality of cores based on the trigger signal.

A system on chip comprising:

• a central processing unit cluster comprising a plurality of first cores, each of which comprises a first dynamic power monitor circuit configured to obtain a first monitoring result based on filtered values by filtering first power classification values provided by the first dynamic power monitor circuit of each of the plurality of first cores, and identify transition values based on difference values between the filtered values of each of the plurality of first cores;
• a graphics processing unit cluster comprising a plurality of second cores, each of which comprises a second dynamic power monitor circuit configured to obtain a second monitoring result based on filtered values by filtering second power classification values provided by the second dynamic power monitor circuit of each of the plurality of second cores, and identify transition values based on difference values between the filtered values of each of the plurality of second cores;
• a first internal voltage regulator configured to scale a first operating voltage provided to the plurality of first cores based on the first monitoring result, according to a first clock signal;
• a first clock manager circuit configured to scale the first clock signal provided to the plurality of first cores based on the first monitoring result;
• a second internal voltage regulator configured to scale a second operating voltage provided to the plurality of second cores based on the second monitoring result, according to a second clock signal;
• and
• a second clock manager circuit configured to scale the second clock signal provided to the plurality of second cores based on the second monitoring result.