Integrated circuit chip and test method thereof

An integrated circuit chip, comprising:

• a first chip circuit, comprising a plurality of first internal pads, a plurality of second internal pads and a current sensor circuit, wherein the current sensor circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pacts;
• a plurality of external pins, coupled to the plurality of first internal pads;
• and
• a second chip circuit, comprising a plurality of third internal pads, wherein the plurality of third internal pads are coupled to the plurality of second internal pads through a plurality of internal traces,
• wherein the current sensor circuit is configured to sense a current transmitted between at least one of the plurality of second internal pads and at least corresponding one of the plurality of third internal pads of the second chip circuit, and generate a corresponding sensing voltage to the one of the plurality of first internal pads.

A test method for an integrated circuit chip, wherein the integrated circuit chip comprises a first chip circuit, a second chip circuit and a plurality of external pins, wherein a plurality of first internal pads of the first chip circuit are coupled to the plurality of external pins, the first chip circuit further comprises a plurality of second internal pads, and the second chip circuit comprises a plurality of third internal pads, wherein a current mirror circuit in the first chip circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pads, wherein the test method comprises:

• selectively and individually operating the plurality of second internal pads in an input state or an output state, and outputting a current to one of the plurality of external pins through the one of the plurality of first internal pads by the current mirror circuit mirroring and summing, a plurality of currents transmitted by the plurality of second internal pads;
• and
• detecting the current transmitted by the one of the plurality of external pins to determine whether the integrated circuit chip is defective,
• wherein the plurality of third internal pads are coupled to the plurality of second internal pads through a plurality of internal traces,
• wherein the current mirror circuit is configured to mirror a current transmitted between at least one of the plurality of second internal pads and at least corresponding one of the plurality of third internal pads of the second chip circuit, and generate a corresponding mirror current to the one of the plurality of first internal pads.

A test method for an integrated circuit chip, wherein the integrated circuit chip comprises a first chip circuit, a second chip circuit and a plurality of external pins, wherein a plurality of first internal pads of the first chip circuit are coupled to the plurality of external pins, the first chip circuit further comprises a plurality of second internal pads, and the second chip circuit comprises a plurality of third internal pads, wherein a current sensor circuit in the first chip circuit is coupled to one of the plurality of first internal pads and the plurality of second internal pads, wherein the test method comprises:

• selectively and individually operating the plurality of second internal pads in an input state or an output state, and outputting a voltage to one of the plurality of external pins through the one of the plurality of first internal pads by the current sensor circuit sensing a plurality of currents transmitted by the plurality of second internal pads;
• and
• detecting the voltage provided by the one of the plurality of external pins to determine whether the integrated circuit chip is defective,
• wherein the plurality of third internal pads are coupled to the plurality of second internal pads through a plurality of internal traces,
• wherein the current sensor circuit is configured to sense a current transmitted between at least one of the plurality of second internal pads and at least corresponding one of the plurality of third internal pads of the second chip circuit, and generate a corresponding sensing voltage to the one of the plurality of first internal pads.