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US 11,442,480 B2Granted
Power supply circuit alternately switching between normal operation and sleep operation
AssigneeLapis Semiconductor Co., Ltd.
InventorsToru Yoshioka, Yoichi Fueki
Life of this patent
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Abstract
A power supply circuit in which an increase in a leakage current can be suppressed is provided. In a power supply circuit in which a main LDO unit outputs a first internal voltage during a normal operation and a sub LDO unit outputs a sleep voltage during a sleep operation, the sleep voltage is applied to a drain of a transistor, and an external voltage higher than the sleep voltage is applied to a gate and a back gate thereof.
Claims2
A power supply circuit which switches to a sleep operation following a normal operation, the power supply circuit comprising;
- a sub low dropout (LDO) unit which generates a sleep voltage that is a voltage for the sleep operation and outputs the sleep voltage to an output terminal during the sleep operation;
- and
- a main LDO unit, comprising:
- a first PMOS transistor having a source connected to a first internal voltage and having a drain connected to the output terminal, and configured to output a second internal voltage, which is a voltage of the drain defined by control of a magnitude of a current flowing between the source and the drain according to a magnitude of a voltage applied to a gate, to the output terminal during the normal operation, wherein
- another voltage higher than the sleep voltage applied to the drain and higher than the first internal voltage applied to the source is applied to the gate and a back gate of the first PMOS transistor to turn a body diode of the first PMOS transistor into a cut-off state during the sleep operation.
2 more elements
Dependencies are inferred from the claim text.