Isolation logic test circuit and associated test method

An integrated circuit comprising:

• a first power domain comprising:
• a power-on-reset (POR) circuit configured to generate a POR signal, wherein the POR circuit is configured to assert the POR signal when a first supply voltage of the first power domain reaches a predetermined threshold;
• a first isolation cell comprising a signal input, a signal output, and a control input, wherein the first isolation cell is configured to be enabled or disabled based on the control input of the first isolation cell,
• a first selection circuit having a first input configured to receive a first functional signal, a second input configured to receive a first test signal, and an output coupled to the control input of the first isolation cell, and
• a second selection circuit having a first input configured to receive the POR signal, a second input configured to receive a second test signal, and an output coupled to the signal input of the first isolation cell;
• a second power domain comprising:
• a test controller having an input coupled to the signal output of the first isolation cell,
• a first pin or pad coupled to a first intermediate node that is coupled between the signal output of the first isolation cell and the input of the test controller, and
• a second pin or pad coupled to an output of the test controller;
• wherein the integrated circuit comprises a plurality of functional modes, and a first test mode;
• wherein, for each of the plurality of functional modes, the first power domain is configured to be on when the second power domain is on, and the second power domain is configured to be off in at least one functional mode in which the first power domain is configured to be on;
• wherein, when the integrated circuit is in the first test mode, the first selection circuit is configured to provide the first test signal to the control input of the first isolation cell, and the second selection circuit is configured to provide the second test signal to the signal input of the first isolation cell;
• and
• wherein, when the integrated circuit is in any of the plurality of functional modes, the first selection circuit is configured to provide the first functional signal to the control input of the first isolation cell, and the second selection circuit is configured to provide the POR signal to the signal input of the first isolation cell.

A method for testing an integrated circuit having a plurality of power domains, a plurality of functional modes, and a first test mode, the method comprising, during the first test mode:

• causing a first selection circuit having a first input for receiving a first functional signal, a second input for receiving a first test signal, and an output coupled to a control input of a first isolation cell, to deliver the first test signal to the control input of the first isolation cell;
• causing a second selection circuit having a first input for receiving a second functional signal, a second input for receiving a second test signal, and an output coupled to a signal input of the first isolation cell, to deliver the second test signal to the signal input of the first isolation cell, wherein a first power domain of the plurality of power domains comprises the first and second selection circuits and the first isolation cell;
• setting the second test signal to logic 1;
• asserting the first test signal to enable the first isolation cell;
• after setting the second test signal to logic 1 and asserting the first test signal, measuring a first voltage at a first pin or pad coupled to a signal output of the first isolation cell, wherein a second power domain of the plurality of power domains comprises the first pin or pad, wherein, for each of the plurality of functional modes, the first power domain is on when the second power domain is on, and the second power domain is off in at least one functional mode in which the first power domain is on;
• setting the second test signal to logic 0;
• deasserting the first test signal to disable the first isolation cell;
• after setting the second test signal to logic 0 and deasserting the first test signal, measuring a second voltage at the first pin or pad;
• setting a first test bit of the first power domain to logic 0, wherein the first test bit is coupled to a first input of an OR gate, the OR gate having a second input coupled to the signal output of the first isolation cell and to the first pin or pad, and an output coupled to an input of a test controller, wherein the second power domain comprises the OR gate and the test controller;
• after setting the second test signal to logic 0, deasserting the first test signal, and setting the first test bit to logic 0, measure a third voltage at a second pin or pad coupled to an output of the test controller, wherein the second power domain comprises the second pin or pad;
• when the first voltage corresponds to logic 0, the second voltage correspond to logic 0, and the third voltage is indicative of the test controller being in reset mode, generating a first indication that a first path coupled to the signal input of the first isolation cell does not have stuck-at 1 faults, and that a second path coupled to the signal output of the first isolation cell does not have stuck-at 1 faults;
• when the first voltage corresponds to logic 0 and the second voltage correspond to logic 1, generating a second indication that the first path has a stuck-at 1 fault;
• and
• when the first voltage corresponds to logic 0, the second voltage correspond to logic 0, and the third voltage is indicative of the test controller not being in reset mode, generating a third indication that the second path has a stuck-at 1 fault.