System-on-chip for AT-SPEED test of logic circuit and operating method thereof

A system-on-chip, comprising:

• a first core including:
• an output port;
• a first scan register receiving scan data;
• a first inverting circuit on a feedback path of the first scan register;
• and
• a logic circuit connected between an output terminal of the first scan register and the output port;
• and
• a second core including an input port connected to the output port of the first core, wherein:
• in a test mode for an AT-SPEED test of the logic circuit, the first inverting circuit generates test data by inverting the scan data that are output from the first scan register,
• the first scan register stores the test data in response to a first pulse of a clock signal, and
• the logic circuit generates result data based on the test data that are output from the first scan register.

An operating method of a system-on-chip including a first scan register, an inverting circuit, and a logic circuit, the method comprising:

• outputting, by the first scan register, scan data in response to a clock signal having a first frequency;
• providing the first scan register with test data generated by inverting the scan data that are output from the first scan register;
• outputting, by the first scan register, the test data in response to a first pulse of the clock signal having a second frequency;
• and
• outputting, by the logic circuit, result data based on the test data that are output from the first scan register.