Droop detection
AssigneeGraphcore Limited
InventorsStephen Felix, Daniel John Pelham Wilkinson
Life of this patent
Estimating the term…
Abstract
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.
Claims17
A method for detecting voltage droop in a supply voltage for a processor, the method comprising:
- receiving at a tap sampled delay line, a first clock signal, wherein the tap sampled delay line is powered by a same power supply that supplies the supply voltage to the processor;
- splitting the first clock signal along two different paths in the tap sampled delay line;
- producing a set of samples of the first clock signal by, along each of the two different paths, upon receipt of an edge of a sample clock signal, sampling the first clock signal at each of a set of taps in the respective path, wherein each of the taps in the respective path is separated by two inverter delays such that the set of samples represent sample values of the first clock signal each separated by a single inverter delay without inversion of the first clock signal between the samples;
- and
- determining a magnitude of the voltage droop by measuring from the set of samples, a change in a clock edge position of the first clock signal,
- wherein the sample clock signal has a same frequency as the first clock signal, and wherein the first clock signal is also received from a further delay line, wherein the further delay line has coarser delay stages than the tap sampled delay line to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.
An apparatus for detecting voltage droop in a supply voltage for a processor, the apparatus comprising a tap sampled delay line comprising:
- an input for receiving at the tap sampled delay line, a first clock signal, wherein the tap sampled delay line is powered by a same power supply that supplies the supply voltage to the processor;
- two different clock paths, each configured to propagate the first clock signal as a differential clock signal;
- a plurality of taps arranged along each of the two different clock paths in the tap sampled delay line, the plurality of taps configured to produce a set of samples of the first clock signal by sampling the first clock signal, wherein along each of the different clock paths, each of the taps in a respective path is separated by at least two inverter delays;
- and
- circuitry configured to determine a magnitude of the voltage droop by measuring a change in a clock edge position of the first clock signal from the set of samples,
- wherein a sample clock signal has a same frequency as the first clock signal, wherein the apparatus comprises a further delay line having coarser delay stages than the tap sampled delay line, wherein the tap sampled delay line is configured to receive the first clock signal from the further delay line, and wherein the further delay line is configured to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.
A method for determining a magnitude of voltage droop in a supply voltage for a processor, the method comprising:
- receiving a first clock signal at a tap sampled delay line that is powered by a same power supply that supplies the supply voltage to the processor;
- splitting the first clock signal along a first path in the tap sampled delay line and a second path in the tap sampled delay line;
- producing a set of samples of the first clock signal along the first path and the second path, including sampling the first clock signal at a plurality of taps in the first path and the second path, wherein each tap of the plurality of taps is separated by two inverter delays;
- and
- measuring a change in a clock edge position of the first clock signal from the set of samples,
- wherein a sample clock signal has a same frequency as the first clock signal, wherein the first clock signal is also received from a further delay line, wherein the further delay line has coarser delay stages than the tap sampled delay line to delay the first clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line.
Dependencies are inferred from the claim text.