Three-dimensional semiconductor devices and methods of fabricating the same

A three-dimensional semiconductor device, comprising:

• a conductive layer disposed on a substrate;
• an insulating base layer disposed on the conductive layer and having a plurality of support regions in contact with the substrate;
• a stack structure having a plurality of gate electrodes and a plurality of mold insulating layers alternately disposed on the insulating base layer;
• a vertical structure including a vertical channel layer penetrating through the stack structure, and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having a first extended area extending in a width direction in the insulating base layer and having a convex side;
• and
• an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, extending in a first direction parallel to an upper surface of the substrate, and having a second extended area extending in a second direction intersecting the first direction and parallel to the upper surface of the substrate in the insulating base layer,
• wherein the conductive layer has a first extension portion extending along a surface of the vertical channel layer, and an upper end of the first extension portion is connected to a lower end of the vertical insulating layer on the surface of the vertical channel layer in the first extended area of the vertical structure,
• wherein the vertical structure further comprises an insulating core disposed in a direction perpendicular to the upper surface of the substrate in the vertical channel layer, and the insulating core has a second extension portion extending in the width direction in the insulating base layer.

A three-dimensional semiconductor device, comprising:

• a conductive layer disposed on a substrate and including a first conductivity type impurity;
• an insulating layer disposed on the conductive layer;
• a stack structure including a lower insulating film disposed on the insulating layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating layer includes a high dielectric material;
• a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having a first area in the insulating layer, wherein a side of the first area in the insulating layer overlaps a lowermost gate electrode of the gate electrodes in a direction perpendicular to an upper surface of the substrate;
• and
• a conductive film extending from the conductive layer and covering at least a bottom surface of the vertical channel layer in the first area, wherein the conductive film includes the first conductivity-type impurity,
• wherein the vertical structure further comprises an insulating core disposed in a direction perpendicular to the upper surface of the substrate in the vertical channel layer, and the insolating core has an extended portion extending in the width direction in the insulating base layer.