US 11,362,666 B2Granted

Low-jitter frequency division clock clock circuit

AssigneeNo. 24 Research Institute of China Electronics Technology Group Corporation

InventorsTao Liu, Jian'an Wang, Yuxin Wang, Guangbing Chen, Dongbing Fu, Ruzhang Li, Shengdong Hu, Zhengping Zhang, Jun Luo, Daiguo Xu, Minming Deng, Yan Wang

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Abstract

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

A low-jitter frequency division clock circuit, comprising:

a clock control signal generation circuit, to generate clock signals having different phases;
a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal;
a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal;
and a frequency division clock generation circuit, to generate a frequency division clock signal according to the low-level narrow pulse width clock control signal and the high-level narrow pulse width clock control signal;
wherein an input end of the clock control signal generation circuit is connected with an input end of a clock input signal;
an output end of the clock control signal generation circuit is respectively connected with an input end of the low-level narrow pulse width clock control signal generation circuit and an input end of the high-level narrow pulse width clock control signal generation circuit;
an output end of the low-level narrow pulse width clock control signal generation circuit and an output end of the high-level narrow pulse width clock control signal generation circuit are connected with an input end of the frequency division clock generation circuit, respectively;
wherein the clock signals having different phases generated by the clock control signal generation circuit includes a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, respectively;
the input end of the clock input signal, the first clock signal and the third clock signal are respectively connected with the input end of the low-level narrow pulse width clock control signal generation circuit;
the input end of the clock input signal, the second clock signal and the fourth clock signal are respectively connected with the input end of the high-level narrow pulse width clock control signal generation circuit.

7 more elements

Facts

Application

17/264,298Filed 13 Dec 2018

Priority

CN 201810877178.23 Aug 2018

Published

US 2021/0297080 A123 Sep 2021

Granted

14 Jun 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H03K 23/44
Out-of-phase gating or clocking signals applied to counter stages: using field-effect transistors
H03K 3/356017
Bistable circuits: using additional transistors in the input circuit
H03K 5/15026
With more than two outputs: with asynchronously driven series connected output stages
H03K 23/42
Gating or clocking signals applied to all stages, i.e. synchronous counters: out-of-phase gating or clocking signals applied to counter stages

Abstract

Claims15