Bus transceiver with ring suppression

A transceiver, comprising:

• a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal;
• and
• a transient-triggered ring suppression circuit coupled to the first and second transistors, the transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state and, while the transceiver is in the recessive state, to attenuate ringing on at least one of the first or second bus terminals;
• wherein the transient-triggered ring suppression circuit includes:
• a third transistor coupled between a terminal of the second transistor and a common voltage terminal, the third transistor having a control input and first and second current terminals;
• a first capacitor coupled between the second current terminal of the third transistor and the control input of the third transistor;
• a first resistor coupled between the ground and the control input of the third transistor;
• and
• a first switch coupled between the ground and the control input of the third transistor.

A transceiver, comprising:

• a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal;
• and
• a transient-triggered ring suppression circuit coupled to the first and second transistors, the transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state and, while the transceiver is in the recessive state, to attenuate ringing on at least one of the first or second bus terminals;
• wherein the transient-triggered ring suppression circuit includes:
• a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals;
• a first capacitor coupled between the first current terminal and the control input of the third transistor;
• a first resistor coupled between the supply voltage terminal and the control input of the third transistor;
• and
• a first switch coupled between the supply voltage terminal and the control input of the third transistor.

A transceiver, comprising:

• a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal;
• a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals;
• a first capacitor coupled between the first current terminal and the control input of the third transistor;
• a first resistor coupled between the supply voltage terminal and the control input of the third transistor;
• a first switch coupled between the supply voltage terminal and the control input of the third transistor;
• a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals;
• a second capacitor coupled between the first current terminal of the fourth transistor and the control input of the fourth transistor;
• a second resistor coupled between the ground and the control input of the fourth transistor;
• and
• a second switch coupled between the ground and the control input of the fourth transistor.