Error correction circuit and memory controller having the same

An error correction circuit, comprising:

• an error correction decoder configured to perform error correction decoding on a read vector on a column layer basis while sequentially selecting column layers of a parity check matrix including a plurality of sub-matrices, wherein the column layer includes a set of columns of the parity check matrix, and
• wherein the error correction decoder includes:
• a plurality of memory areas configured to store values of a plurality of check nodes corresponding to the parity check matrix;
• and
• a check node processor including a plurality of check node units and configured to access one or more of the plurality of memory areas corresponding to cyclic permutation matrices (CPMs) included in a currently selected column layer, and update values of check nodes stored in the accessed one or more memory areas,
• wherein rows included in the parity check matrix are grouped into a plurality of row groups, and at most one CPM is included for each column layer in each of the row groups, and
• wherein the plurality of check node units for the currently selected column layer does not access two or more memory areas.