Gain and memory error estimation in a pipeline analog to digital converter

A pipeline ADC (analog to digital converter) comprising a plurality of stages, and at least one stage comprising:

• a flash ADC configured to receive an input signal and configured to generate a flash output;
• a DAC (digital to analog converter) coupled to the flash ADC and configured to generate a coarse signal in response to the flash output;
• a subtractor coupled to the DAC and configured to generate a residue signal in response to the coarse signal and the input signal;
• and
• a gain amplifier coupled to the subtractor and configured to generate an amplified signal in response to the residue signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator comprises a first comparator, a second comparator and a decision block, the decision block configured to receive a PRBS (pseudo random binary sequence) signal.

A method comprising:

• comparing an input signal and a primary threshold to generate a first signal, the input signal is received at a positive input terminal and the primary threshold signal is received at a negative input terminal of a first comparator;
• comparing the input signal and the primary threshold to generate a second signal, the input signal is received at a positive input terminal and the primary threshold signal is received at a negative input terminal of a second comparator;
• and
• generating a control signal in response to the first signal and the second signal.

A method of gain error estimation in a pipeline ADC, the pipeline ADC comprising a plurality of stages, comprising:

• generating a flash output in response to an input signal by a flash ADC;
• generating a coarse signal in response to the flash output;
• subtracting the coarse signal from the input signal to generate a residue signal;
• and
• amplifying the residue signal to generate an amplified signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator configured to receive a PRBS (pseudo random binary sequence) signal and comprises a first comparator, a second comparator and a logic gate.

A computing device comprising:

• a processing unit;
• a memory module coupled to the processing unit;
• and
• a logic unit coupled to the processing unit and the memory module, the logic unit comprising a stochastic comparator, the stochastic comparator comprising:
• a first comparator configured to compare an input signal and a primary threshold to generate a first signal;
• a second comparator configured to compare the input signal and the primary threshold to generate a second signal;
• and
• a decision block configured to generate a control signal in response to the first signal and the second signal.