Monitor circuitry for power management and transistor aging tracking
AssigneeIntel Corporation
InventorsKuan-Yueh Shen, Nasser A. Kurd, John Fallin
Life of this patent
Estimating the term…
Abstract
Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
Claims17
An apparatus comprising:
- a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage;
- an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node;
- a second path including a frequency divider coupled to the second node and the phase frequency detector;
- and
- a circuit to generate digital information having a value based on a value of the voltage at the second node.
An apparatus comprising:
- a phase frequency detector to receive a first signal having a first frequency, a charge pump coupled to the phase frequency detector, a filter coupled to the charge pump, and a circuit coupled to the filter, the circuit including a circuit node to provide a voltage;
- a first circuit to generate a first oscillating signal, the first circuit including a first node, and a first additional node to provide the first oscillating signal;
- a second circuit to generate a second oscillating signal, the second circuit including a second node, and a second additional node to provide the second oscillating signal;
- a first switch coupled between the circuit node and the first node of the first circuit;
- a second switch coupled between the circuit node and the second node of the second circuit;
- a frequency divider coupled between the phase frequency detector and each of the first additional node and the second additional node;
- and
- an analog-to-digital converter coupled to circuit node.
An apparatus comprising:
- a first circuit on a die and a second circuit on the die;
- a phase frequency detector on a circuit path on the die to receive a first signal having a first frequency, the circuit path including a circuit node to provide a voltage;
- a first additional circuit on the die and coupled to the circuit node, the first additional circuit including replica of the first circuit, and a first output node to provide a first oscillating signal;
- a second additional circuit on the die and coupled to the circuit node, the second additional circuit including a replica of the second circuit, and a second output node to provide a second oscillating signal;
- a frequency divider coupled to the phase frequency detector and to each of the first and second output nodes;
- and
- an analog-to-digital converter coupled to circuit node.
An apparatus comprising:
- a processor including a processing circuitry and a phase locked loop coupled to the processing circuitry, the processing circuitry including a logic circuit path, the phase locked loop including:
- a first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage;
- an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node;
- a second path including a frequency divider coupled to the second node and the phase frequency detector;
- and
- a circuit to generate digital information having a value based on a value of a voltage at the second node.
Dependencies are inferred from the claim text.