Reconfigurable logic circuit

A reconfigurable logic circuit comprising:

• a first switching circuit arranged for receiving a first input bit and at least one first configuration bit, a second switching circuit arranged for receiving a second input bit and at least one second configuration bit, and a third switching circuit arranged for receiving a third input bit and at least one third configuration bit, said switching circuits arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit,
• a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit,
• a fourth switching circuit arranged for receiving a fourth input bit and at least one fourth configuration bit, a fifth switching circuit arranged for receiving a fifth input bit and at least one fifth configuration bit, and a sixth switching circuit arranged for receiving a sixth input bit and at least one sixth configuration bit, and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit,
• a first, second and third AND logic block, each arranged for receiving a different pair of outputs formed from the outputs of said fourth, fifth and sixth switching circuit,
• a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit;
• wherein each of the first, the second, the third, the fourth, the fifth and the sixth switching circuits are arranged for receiving only one input bit,
• wherein the configuration bits are provided for programming the functionality of the logic circuit relative to the input bits.

A reconfigurable logic circuit comprising:

• a first switching circuit arranged for receiving a first input bit and at least one first configuration bit, a second switching circuit arranged for receiving a second input bit and at least one second configuration bit, and a third switching circuit arranged for receiving a third input bit and at least one third configuration bit, said switching circuits arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit,
• a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit,
• a fourth switching circuit arranged for receiving a fourth input bit and at least one fourth configuration bit, a fifth switching circuit arranged for receiving a fifth input bit and at least one fifth configuration bit, and a sixth switching circuit arranged for receiving a sixth input bit and at least one sixth configuration bit, and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit,
• a first, second and third AND logic block, each arranged for receiving a different pair of outputs formed from the outputs of said fourth, fifth and sixth switching circuit,
• a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit;
• wherein a number of switching circuits in the reconfigurable logic circuit is equal to a number of input bits,
• wherein the configuration bits are provided for programming the functionality of the logic circuit relative to the input bits.