Level shifting circuit

A level shifting circuit, comprising:

• a first inverter adapted to invert an input signal received by an input node of the level shifting circuit and output an inverted input signal to a second input node of a level shifting unit, an input node of the first inverter being coupled to the input node of the level shifting circuit, and an output node of the first inverter being coupled to the second input node of the level shifting unit;
• the level shifting unit adapted to perform amplitude up-shifting processing on the input signal received by the input node of the level shifting circuit, a first input node of the level shifting unit being coupled to the input node of the level shifting circuit, the second input node of the level shifting unit being coupled to the output node of the first inverter, a first power node of the level shifting unit being coupled to a first power voltage, and a second power node of the level shifting unit being coupled to a second power voltage, wherein:
• the level shifting unit comprises a first N-type metal-oxide-semiconductor (NMOS) transistor, a second NMOS transistor, a first P-type metal-oxide-semiconductor (PMOS) transistor, and a second PMOS transistor,
• a gate terminal of the first NMOS transistor being coupled to the first input node of the level shifting unit, a source terminal of the first NMOS transistor being coupled to the first power node, and a drain terminal of the first NMOS transistor being coupled to a drain terminal of the first PMOS transistor;
• the drain terminal of the first PMOS transistor being further coupled to a gate terminal of the first PMOS transistor and to a gate terminal of the second PMOS transistor, and a source terminal of the first PMOS transistor being coupled to the second power node;
• a source terminal of the second PMOS transistor being coupled to the second power node, and a drain terminal of the second PMOS transistor being coupled to the output node of the level shifting unit;
• and
• a gate terminal of the second NMOS transistor being coupled to the output node of the first inverter, a source terminal of the second NMOS transistor being coupled to the first power node, and a drain terminal of the second NMOS transistor being coupled to the output node of the level shifting unit;
• and
• a fast driving unit adapted to pull up an output signal of an output node of the level shifting unit by increasing a discharge current of the level shifting unit when receiving the input signal, wherein:
• the fast driving unit comprises a first fast driving subunit and a second fast driving subunit,
• the first fast driving subunit being adapted to increase a discharge current of a discharge path between the second power node and the first power node in response to an input signal of an input node of the level shifting unit being a high-level signal;
• and
• the second fast driving subunit being adapted to increase a discharge current of a discharge path between the output node of the level shifting unit and the first power node in response to the input signal of the input node of the level shifting unit being a low-level signal.